| 摘要 |
A technique for verifying an intermediate node that employs a forwarding pla ne (572a, 572b) and optionally a control plane (592a, 592b). A test packet is generated and transferred to the for~warding plane (572a, 572b). Using operational software and hardware, the forwarding plane (572a, 572b) for~war ds the test packet to a line card (512a, 512b), which in turn "loops" (700a, 700b, 700c) the test packet back to the forwarding-plane (572a, 572b). Using operational software and hardware, the forwarding plane (572a, 572b) pro~cesses the looped-back test packet including forwarding the packet to a destination, such as a control plane (592a, 592b), where the looped-back tes t packet is verified.
|
