发明名称 |
High performance interconnect architecture for FPGAs |
摘要 |
<p>A high performance interconnect architecture is described that provides reduced delay minimized electromigration and reduced area in FPGAs comprising a plurality of tiles consisting of interconnected logic blocks, that are separated by intervening logic blocks. Each set of interconnected logic blocks is linked by an interconnect segment that is routed in a straight line through an interconnect layer over intervening logic blocks and is selectively connected to the logic block at each end through a connecting segment.</p> |
申请公布号 |
EP1432126(A2) |
申请公布日期 |
2004.06.23 |
申请号 |
EP20030104727 |
申请日期 |
2003.12.16 |
申请人 |
STMICROELECTRONICS PVT. LTD. |
发明人 |
BAL, ANKUR;KHANNA, NAMERITA |
分类号 |
H03K19/177;(IPC1-7):H03K19/177 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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