| 摘要 |
Two resistors R1 and R2 are connected in parallel between a charging power source BAT1 and an electric dual-layered capacitor C1. An FET Q1 is connected to one of the resistors R2 in series. The gate of the FET Q1 is connected to the drain of an FET Q2. The inter-terminal voltage of the electric dual-layered capacitor is divided by resistors R3 and R4 and applied to the gate of the FET Q2. At charging start, current flows to the electric dual-layered capacitor via the resistor R1. When the potential of the electric dual-layered capacitor is increased to a certain degree and the charging current is lowered, the FET Q1 and Q2 turn on and the two resistors R1 and R2 operate in parallel. Thus, the charging current increases again, thereby reducing the charging time and the power consumption. |
