发明名称 Refresh techniques for memory data retention
摘要 A digital memory system (30) includes a memory cell (52), a bit line (50) and a charge integrity estimating module 35. The module is operative during a first mode of operation to detect whether a quantity of the charge stored in the memory cell lies within the first range of values or the second range of values, is operative during a second mode of operation to detect whether the quantity of the charge lies within a third range of values comprising a subset of the first range of values and is operative during a third mode of operation to detect whether the quantity of the charge lies within a fourth range of values comprising a subset of the second range of values.
申请公布号 US6754101(B2) 申请公布日期 2004.06.22
申请号 US20030423350 申请日期 2003.04.25
申请人 BROADCOM CORPORATION 发明人 TERZIOGLU ESIN;AFGHAHI MORTEZA CYRUS;WINOGRAD GIL I.
分类号 G11C16/04;(IPC1-7):G11C16/04;G11C16/06 主分类号 G11C16/04
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