发明名称 |
System and method for managing vertical dependencies in a digital signal processor |
摘要 |
An apparatus for managing vertical dependencies between instructions in first and second instruction pipelines includes: 1) identifier (ID) reclaim circuitry for determining a sequential set of retired identifiers associated with retired instructions and for determining a next retire ID sequentially following the set; 2) first ID generation circuitry for sequentially assigning identifiers to destination registers associated with instructions entering the pipelines; 3) second ID generation circuitry associated with the first pipeline for identifying a first dependent source register associated with a first dependent source operand of a first instruction entering the first pipeline and assigning an ID of the first register to the first operand; and 4) instruction scheduling circuitry for comparing the first operand ID of the first instruction with the next retire ID and scheduling the first instruction for execution if the first operand ID is less than or equal to the next retire ID. |
申请公布号 |
US6754807(B1) |
申请公布日期 |
2004.06.22 |
申请号 |
US20000652450 |
申请日期 |
2000.08.31 |
申请人 |
STMICROELECTRONICS, INC. |
发明人 |
PARTHASARATHY SIVAGNANAM;DRIKER ALEXANDER |
分类号 |
G06F9/34;G06F9/38;G06F9/445;(IPC1-7):G06F9/34 |
主分类号 |
G06F9/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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