| 摘要 |
A memory control circuit for controlling a memory bus and a memory includes buffers, counters, data transfer circuits, and a bus arbiter having a state machine. Each of the data transfer circuits transmits a request signal demanding start of the data transfer on the basis of at least one of the count values of the counters. If the data transfer circuit associated with the current state transmits the request signal, the bus arbiter transmits an acknowledge signal granting start of the data transfer. Each of the data transfer circuits starts the data transfer at receipt of the acknowledge signal, and stops the data transfer being executed on the basis of either number of pieces of data transferred after the receipt of the acknowledge signal or the count value of at least one of the counters. When the data transfer circuit associated with the current state either does not transmit the request signal or has stopped the data transfer, the bus arbiter does not transmit the acknowledge signal to the data transfer circuit associated with the current state, and transition of the current state takes place in accordance with the predetermined transition condition.
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