| 摘要 |
Disclosed is an apparatus and method for driving a ferroelectric memory that can secure an enough read/write cycle time of a corresponding address during a chip is driven. In a driving circuit to generate an operation pulse for controlling operation of a ferroelectric chip, the ferroelectric memory driving apparatus includes an address latch block for latching a buffered address signal by a feedback cell operation pulse, an address transition detection summation value outputting block for generating an address transition detection pulse by detecting change of an address signal, and for outputting summation of address transition pulses generated by a plurality of addresses, a pulse width extension/control pulse generating block for extending a pulse width of the summation of the address transition pulses and outputting a chip control pulse by using an extended signal, and a cell operation pulse generating block for generating a cell operating pulse with a pulse width required on a read/write chip operation by using the chip control pulse, wherein in an active region of the cell operation pulse corresponding the address, an ATD signal of a different address is not generated.
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