| 摘要 |
A P-well region and an N-well region are formed in an upper layer of a silicon wafer. A shallow trench having a depth of 0.05 mum to 0.1 mum is formed in the vicinity of a boundary between the P-well region and the N-well region. A gate oxide film is formed on an entire surface of the silicon wafer. On a bottom of the shallow trench of the P-well region and the outer layer of the silicon wafer contacting the upper ends of the sidewall of the shallow trench are formed n<+>-diffusion layers. On the bottom of the shallow trench of the N-well region and the outer layer of the silicon wafer contacting the upper ends of the sidewall of the shallow trench are formed p<+>-diffusion layers. On the sidewalls of the shallow trench, gate electrodes are formed through the gate oxide film. A silicon oxide film is formed so as to cover the gate electrodes. Electrodes contacting the diffusion layers are formed through the silicon oxide film.
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