发明名称 |
Topography correction for testing of redundant array elements |
摘要 |
A data topography correction circuit for a semiconductor memory device and method for testing the device is provided. The data topography correction circuit includes a redundant hit circuit for determining if a redundant element has been used to replace a defective element; and a redundant topology correction scrambler circuit for converting data from a data topology of the defective element to a data topology of the redundant element. The method includes the steps of providing an address of a memory array element of the device to be tested; determining if the memory array element has been replaced with a redundant element; and, if the memory array element has been replaced, correcting test data to the data topology of the redundant element.
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申请公布号 |
US6754113(B2) |
申请公布日期 |
2004.06.22 |
申请号 |
US20020253148 |
申请日期 |
2002.09.24 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
MA DAVID SUITWAI;BRUCKE PAUL EDWARD |
分类号 |
G11C29/00;G11C29/24;(IPC1-7):G11C7/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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