| 发明名称 |
USE OF SILICON BLOCK PROCESS STEP TO CAMOUFLAGE A FALSE TRANSISTOR |
| 摘要 |
A technique for and structures for camouflaging an integrated circuit structure. A layer of conductive material having a controlled outline is disposed to provide artifact edges of the conductive material that resemble an operable device when in fact the device is not operable. |
| 申请公布号 |
AU2003293038(A1) |
申请公布日期 |
2004.06.18 |
| 申请号 |
AU20030293038 |
申请日期 |
2003.11.20 |
| 申请人 |
HRL LABORATORIES, LLC |
发明人 |
JAMES, P. BAUKUS;LAP-WAI CHOW;WILLIAM, M., JR. CLARK;GAVIN, J. HARBISON |
| 分类号 |
H01L23/58;H01L27/02;(IPC1-7):H01L27/02 |
主分类号 |
H01L23/58 |
| 代理机构 |
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代理人 |
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