发明名称 UNIFIED SYNCHRONIZATION BOARD AND METHOD USING DIGITAL PROCESSING-PHASE LOCKED LOOP
摘要 PURPOSE: A unified synchronization board and method using a digital processing-phase locked loop are provided to easily maintain the board as well as to reduce the cost of the installation and the maintenance. CONSTITUTION: A unified synchronization board using a digital processing-phase locked loop includes a mode selection block(27), a control block(23), a digital/analog(D/A) converting block(25) and a clock oscillation block(26). The mode selection block(27) applies the operational mode signal in response to the operational mode of the synchronization board. The control block(23) applies the digital control value corresponding to the system clock frequency control range of the corresponding mode in response to the operational mode signal applied from the mode selection block(27). The D/A converting block(25) converts the digital control valued applied from the control block(23) into an analog voltage. And, the clock oscillation block(26) oscillates the system clock of the corresponding frequency in response to the converted analog voltage.
申请公布号 KR20040051019(A) 申请公布日期 2004.06.18
申请号 KR20020078841 申请日期 2002.12.11
申请人 LG ELECTRONICS INC. 发明人 SUNG, SANG GYEONG
分类号 H04L7/02;(IPC1-7):H04L7/02 主分类号 H04L7/02
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