DELAY GENERATING METHOD, DELAY ADJUSTING METHOD BASED ON THIS METHOD, DELAY GENERATING CIRCUIT BY APPLYING THESE METHODS AND DELAY ADJUSTING CIRCUIT

摘要

PROBLEM TO BE SOLVED: To provide a delay adjusting circuit for performing stable and quick operation for minimizing a delay in a selector part even if the stage number of delays and the stage number of selectors are increased.

SOLUTION: This delay adjusting circuit is constituted in two stages by respective selectors S1, S3 to Sn and Sn +2 for an even number stage and respective selectors S2 to Sn + 1 and Sn + 3 for an odd number stage by using a 2 : 1 selector of a type connected to an input/output place of delay elements D1 to DN of N stages as a constitution of a selector S and selectively outputting one system from input of two systems for delaying and outputting an even number stage delay clock signal Even and an odd number stage delay clock signal Odd by improving the constitution of the selector S in a delay generating circuit 11. The even number stage delay clock signal Even of first output is obtained via the selector S1 of a first stage, and the odd number stage delay clock signal Odd of second output is obtained via the selector S2 of a second stage.

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