Semiconductor memory device for improvement of defective data line relief rate

摘要

A semiconductor memory device according to the present invention includes: a data line switching circuit including a plurality of switches which selectively connect one of a plurality of normal data lines and spare data lines included in a memory cell array to one of a plurality of global data lines for transmitting input/output data to the memory cell array; and a switching control circuit including a shift decoder having decode circuits for decoding a defective address stored in a program circuit as many as the switches.