| 摘要 |
PROBLEM TO BE SOLVED: To find, at a chip level, a contact hole high-density portion on large area wiring where a wiring defect occurs. SOLUTION: In the layout verification method of a semiconductor device for verifying a formation defect which occurs in wiring on a chip layout, an area ratio between the total area of the same node wiring on the chip layout and the total area of a contact hole on the same node wiring is limited and based upon the limitation, propriety is judged to detect the portion where the wiring formation is defective. Thus, the defective portion exceeding the area ratio limitation on a layout design stage is detected, thereby avoiding the formation defect such as large area wiring disconnection, wiring destruction or surface peeling caused by hillock or a connection defect between wiring and the contact hole. COPYRIGHT: (C)2004,JPO
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