发明名称 |
System, method and apparatus for conserving power consumed by a system having a processor integrated circuit |
摘要 |
A processor integrated circuit has at least one processor and two or more levels of cache memory. A first power connection provides power to the processor and lower level cache, which form a first power domain. The integrated circuit has a second power connection providing power to upper level cache of the circuit, forming a second power domain. There may be additional power connections to the integrated circuit, forming additional power domains, such as periphery or memory-interface power.
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申请公布号 |
US2004117678(A1) |
申请公布日期 |
2004.06.17 |
申请号 |
US20020319667 |
申请日期 |
2002.12.13 |
申请人 |
SOLTIS DONALD C.;NAFFZIGER SAMUEL |
发明人 |
SOLTIS DONALD C.;NAFFZIGER SAMUEL |
分类号 |
G06F1/20;G06F1/32;(IPC1-7):G06F1/32 |
主分类号 |
G06F1/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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