MEMORY SYSTEM COMPRISING A PLURALITY OF MEMORY CONTROLLERS AND METHOD FOR SYNCHRONIZING THE SAME

摘要

The invention relates to a memory system which is configured with a pluralit y of memory controllers (SCx), disposed in parallel on a clocked bus (B), and memory chips (Fx) associated with the respective memory controllers (SCx). T he system communicates via the bus (B) with a host system (HS) by means of operational memory commands using logical memory sector numbers. The inventi ve system is characterized in that for any memory operation requested by the ho st system (HS) the memory controller (SCx) affected with respect to a range of logical memory sector numbers (SCx) takes over the bus for communication wit h the host system (HS) by means of arbitration.