Hardware managed virtual-to-physical address translation mechanism

摘要

A hardware managed virtual-to-physical address translation mechanism for a data processing system having no system memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The hard disk contains a virtual-to-physical translation table for translating a virtual address from one of said volatile cache memories to a physical disk address directed to a storage location in the hard disk without transitioning through a real address. The storage controller, which is coupled to a physical memory cache, allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address. The physical memory cache contains a subset of information within the hard disk.