| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an arithmetic processing unit capable of reducing an entire circuit size and power consumption. <P>SOLUTION: The arithmetic processing unit 100 comprises first and second multiplication circuits 111,112 that multiply an input in-phase signal and an input orthogonal signal by -1 each for generating a multiplication in-phase signal and a multiplication orthogonal signal, first and fourth selection circuits 121,124 for receiving the input in-phase signal and the multiplication in-phase signal, and second and third selection circuits 122,123 for receiving the input orthogonal signal and the multiplication orthogonal signal. In the arithmetic processing unit 100, first and second selection signals from the first and second selection circuits 121,122 are added for generating a first complex signal, and third and fourth selection signals from the third and fourth selection circuits 123,124 are added for generating a second complex signal. <P>COPYRIGHT: (C)2004,JPO |
