发明名称 MEMORY CONTROLLER FOR MANAGING DATA IN MEMORY COMPONENT
摘要 <P>PROBLEM TO BE SOLVED: To provide another method alternative to a solution by SRAM and DRAM, with further high performance, further high data transfer rate, and further low cost. <P>SOLUTION: This memory controller comprises a data storage system for transferring data in one of a number of selectable transfer modes. In one embodiment of this data storage system, a memory component comprises a memory controller for managing data within the memory component. The memory controller comprises a switching circuit that has a plurality of data input/output (I/O) terminals and multiple sets of transfer terminals. A standard transfer circuit is connected to one set of transfer terminals and a fast serial transfer circuit is connected to another set of transfer terminals. The memory controller further comprises a compression/decompression engine connected to a data transfer path. <P>COPYRIGHT: (C)2004,JPO
申请公布号 JP2004171561(A) 申请公布日期 2004.06.17
申请号 JP20030381101 申请日期 2003.11.11
申请人 HEWLETT-PACKARD DEVELOPMENT CO LP 发明人 PLINE STEVEN L;SPENCER ANDREW M;ELDREDGE KENNETH J;ALTREE MICHAEL
分类号 G06K19/07;G06F12/00;G06F12/04;G06F13/14;G06F13/16;G11C7/00;G11C7/10;G11C16/00 主分类号 G06K19/07
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