| 摘要 |
<p>Main transistors (M1,M2) are divided into sub-transistors arranged in a matrix with four rows and four columns in such a manner that four cells each are constituted by four sub-transistors having a common center point. This can realize a layout structure wherein the transistor-matching of the main transistors (M1,M2) is as excellent as that of the four-segment layout scheme and wherein the pattern area is small.</p> |
