IMPROVED SYSTEM FOR PROGRAMMING A NON-VOLATILE MEMORY CELL

摘要

An array (40) of dual bit dielectric memory cells (48) comprises a plurality of bit lines. A first bit line (201) forms a source region for each of a plurality of memory cells (38) within a column of memory cells within the array (40). A second bit line (202) forms a drain region for each of the plurality of memory cells (38) within the column. A channel region (50) of the opposite conductivity is positioned between the first bit line (201) and the second bit line (202) and forms a junction with each. A selected word line (211) is positioned over the channel region (50) and forms a gate (60) over each for a plurality of memory cells (48) within a same row. A plurality of non-selected word lines (210, 212), are each parallel to the selected word line (211) and each form a gate (60) over one of the plurality of memory cells (48) within the column other than the selected one of the plurality of memory cells (49). A word line control circuit (46) applies a positive programming voltage (220) to the selected word line (211) while a bit line control circuit (44) simultaneously applies a positive drain voltage to the drain bit line (202) and a positive source voltage to the source bit line (201), the positive source voltage being less than the positive drain voltage.