发明名称 MULTI-CYCLE PATH ANALYZING METHOD
摘要 PROBLEM TO BE SOLVED: To provide an analyzing method for coping with the use of a gated clock and the enlargement of a circuit, shortening a processing time, and accurately detecting a multi-cycle path. SOLUTION: An analysis of a circuit to be analyzed is made in correspondence with a name of each element including a cell for constituting the circuit to be analyzed, the meaning and the relation of a signal to a terminal of the element, and the determination of whether or not the path from a starting point to an end point is the multi-cycle path is made by using the result of the analysis. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004171149(A) 申请公布日期 2004.06.17
申请号 JP20020334069 申请日期 2002.11.18
申请人 FUJITSU LTD 发明人 HIGUCHI HIROYUKI
分类号 G06F17/50;(IPC1-7):G06F17/50 主分类号 G06F17/50
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