DATA COHERENT LOGIC FOR AN SRAM DEVICE

摘要

The present invention provides data coherent logic for an SRAM device. The present invention utilizes a data strobe signal and an output strobe signal to control data written into and read out of the SRAM device from an input/output pad. Data coherent logic is designed to resolve timing conflicts between the data and output strobe signals. The logic selectively delays the output strobe signal when a match occurs for data requested in a read operation immediately following a write operation. The delay allows sufficient time for the data to be registered and selected before being outputted from the device.