发明名称 BUILT-IN SELF-CHECKING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a method of suppressing flip-flops to be not observable irreducible minimum by masking only a part of scan paths concerning a masking method in a built-in self-checking circuit. SOLUTION: The flip-flops 5 with a reset terminal are inserted on the scan paths 3 and the flip-flops 5 with reset terminal are specified by a mask register 4 and are reset, so that the flip-flop values out of the test object for inputting in the flip-flops 5 with reset terminal are initialized and masked. Also, a path bypassing some flip-flops is provided on the scan paths 3 and flip-flops out of the test object are removed from the scan paths. The time of masking the scan path can be specified in the constitution and by masking only at a specific time during shift operation of the scan paths, only the specified flip-flop values are masked. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004170244(A) 申请公布日期 2004.06.17
申请号 JP20020336474 申请日期 2002.11.20
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 AZUMA KENICHIRO;OTA MITSUHO;TAKEOKA SADAMI
分类号 G01R31/28;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
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