发明名称 |
Sublithographic nanoscale memory architecture |
摘要 |
A memory array comprising nanoscale wires is disclosed. The nanoscale wires are addressed by means of controllable regions axially and/or radially distributed along the nanoscale wires. In a one-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires and microscale wires. In a two-dimensional embodiment, memory locations are defined by crossing points between perpendicular nanoscale wires. In a three-dimensional embodiment, memory locations are defined by crossing points between nanoscale wires located in different vertical layers.
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申请公布号 |
US2004113139(A1) |
申请公布日期 |
2004.06.17 |
申请号 |
US20030627406 |
申请日期 |
2003.07.24 |
申请人 |
DEHON ANDRE;LIEBER CHARLES M.;LINCOLN PATRICK D.;SAVAGE JOHN E. |
发明人 |
DEHON ANDRE;LIEBER CHARLES M.;LINCOLN PATRICK D.;SAVAGE JOHN E. |
分类号 |
G11C13/00;G11C8/10;G11C13/02;H01L21/3205;H01L23/52;H01L23/522;H01L27/10;H01L29/06;H01L49/00;(IPC1-7):H01L29/06 |
主分类号 |
G11C13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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