| 摘要 |
A memory device comprising a normal memory cell array and a spare memory cell array, in which memory cells each comprising a ferroelectric capacitor are arranged, a normal word line, a normal word line driver, a spare word line, a spare word line driver, an address input circuit to which an address signal is inputted, and a judging circuit which compares an input address with a faulty address and generates an output for selecting one of the normal and spare word line drivers according to the comparison, wherein the normal and spare word line drivers are simultaneously selected by an output of the address input circuit to start driving the normal and spare word lines, and thereafter the normal and spare word line drivers are enabled by the output of the judging circuit to stop the driving of one of the normal and spare word lines and continue the other.
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