发明名称 HIGH SPEED VITERBI DECODER
摘要 PURPOSE: A high speed Viterbi decoder is provided to allow the pipeline type decoding by the unit of block having various lengths, thereby improving the throughput of the high speed Viterbi decoder. CONSTITUTION: A high speed Viterbi decoder includes a branch metric operational block(202), an add-compare selector(ACS) operational block(203), a normalization operational block(204), a pair of inverse trace storage blocks(206,207), an inverse trace storage control block(208) and an inverse trace block(210). The branch metric operational block(202) calculates the branch matrix. The ACS operational block(203) supplies the path metric value and the inverse trace control information informing the end of the decoding for each block when they are decoded by the unit of block having various lengths. The normalization operational block(204) receives the path metric values for all status outputted from the ACS operational block(203) to normalize the received path metric values and to output the normalized path metric values to the ACS operational block(203). The pair of inverse trace storage blocks(206,207) store the path information outputted from the ACS operational block(203) in the form of block. The inverse trace storage control block(208) controls the two inverse trace storage blocks(206,207) so as to alternatively output the path information stored therein. And, the inverse trace block(210) performs the real decoding by using the path information selected to all status outputted from the two inverse trace storage blocks(206,207).
申请公布号 KR20040050754(A) 申请公布日期 2004.06.17
申请号 KR20020077924 申请日期 2002.12.09
申请人 ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE 发明人 CHAE, SU CHANG;CHOI, JEONG PIL;LEE, YONG SU;PARK, YUN OK
分类号 H03M13/41;(IPC1-7):H03M13/41 主分类号 H03M13/41
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