发明名称 DYNAMIC REAL TIME GENERATION OF 3GPP TURBO DECODER INTERLEAVER SEQUENCE
摘要 An apparatus for dynamic real time generation of interleaver sequences for a decoder includes a vector memory (210) that stores a plurality of vectors (212, 214, 216). Each vector (212, 214, 216) corresponds to a desired reordering of a matrix. A data memory (240) stores individual data elements (242) from a data stream (202) so that each data element (242) is stored in a different memory location in a predetermined order. An interleaver (220) circuit dynamically generates a plurality of interleaver elements (224), each in response to a request signal (226) (being asserted and each pointing to a memory location. A MAP decoder (260) receives the interleaver elements (224) from the interleaver circuit and retrieves the data element (242) stored in a memory location pointed to by each interleaver element (224). The MAP decoder (260) generates a reordered data stream (262) including the data elements (242) ordered in an arrangement corresponding to the sequence in which the interleaver elements (224) are received from the interleaver circuit.
申请公布号 WO2004051864(A2) 申请公布日期 2004.06.17
申请号 WO2003US37152 申请日期 2003.11.19
申请人 MOTOROLA, INC. 发明人 MOLINA, ROBERT, J.
分类号 G11C7/10;H03M13/27;H03M13/29 主分类号 G11C7/10
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