发明名称 |
Clock synchronizing circuit and method |
摘要 |
A delay locked loop for generating a replica clock signal synchronized to an externally generated clock signal comprises a succession of separately controlled delay lines. Each of the delay lines has different delay resolution.
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申请公布号 |
US2004117683(A1) |
申请公布日期 |
2004.06.17 |
申请号 |
US20020319907 |
申请日期 |
2002.12.16 |
申请人 |
WALLER WILLIAM KENNETH |
发明人 |
WALLER WILLIAM KENNETH |
分类号 |
G06F1/12;(IPC1-7):G06F1/12 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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