发明名称 |
Gate-to-electrode connection in a flat panel display |
摘要 |
A flat panel display and manufacturing method therefor is provided having a baseplate hermetically sealed to a faceplate. A first electrode and a resistive layer are formed on the baseplate. An insulating layer is deposited on the resistive layer. A second electrode is formed over the insulating layer. A passivation layer is deposited over the insulating layer and a gate is formed over the passivation layer. Openings are concurrently formed in the gate and insulation layer and used to form an emitter cavity. A conductive glue is deposited to form a gate-to-electrode contact for connecting the gate and the second electrode. An emitter is formed in the emitter cavity and emitter material outside of the emitter cavity is removed.
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申请公布号 |
US6750606(B2) |
申请公布日期 |
2004.06.15 |
申请号 |
US20010947288 |
申请日期 |
2001.09.05 |
申请人 |
SONY CORPORATION;SONY ELECTRONICS, INC. |
发明人 |
KENMOTSU HIDENORI |
分类号 |
H01J9/02;H01J9/26;H01J31/12;(IPC1-7):H01J19/24 |
主分类号 |
H01J9/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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