发明名称 |
Method and system for performing memory repair analysis |
摘要 |
A method and a system for performing memory repair analysis are provided. A merge circuit is connected between test storage device of semiconductor testing equipment and pre-analysis storage device of repair analysis apparatus. Prior to memory repair analysis process, data from a plurality of functional tests are merged as a functional test data with addresses of fail bits by the merge circuit, then stored in pre-analysis storage device for analyzing. Therefore, test time is reduced and test efficiency is improved.
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申请公布号 |
US6751760(B2) |
申请公布日期 |
2004.06.15 |
申请号 |
US20010988518 |
申请日期 |
2001.11.20 |
申请人 |
CHIPMOS TECHNOLOGIES INC. |
发明人 |
TSENG YUAN-PING;WANG VINCENT;CHENG LINCK;LIU AN-HONG |
分类号 |
G11C29/00;(IPC1-7):G11C29/00 |
主分类号 |
G11C29/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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