| 摘要 |
A method of detecting double-symbol errors and correcting single-symbol errors in a data stream being transmitted in a computer system, e.g., from a memory array to a memory controller. The method includes decoding the data stream which was encoded using a logic circuit which had, as inputs, the data being sent and two address parity bits derived from the system address of the data. Data retrieved from the wrong address can be detected by this code. The logic circuit is described by a parity-check matrix for this (146,130) code comprising 128 data bits, 16 check bits, and 2 address parity bits. Although the symbol width of the code is four bits, the code can also be used effectively in memory systems where the memory chip width is eight bits.
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