发明名称 |
Hierarchical creation of vectors for quiescent current (IDDQ) tests for system-on-chip circuits |
摘要 |
A method is presented for generating test vectors for an integrated circuit. Input test vectors and output test vectors are generated for non-core cell portions of the integrated circuit. Input test vectors and output test vectors are generated for core cell partitions of the integrated circuit. The input test vectors for the non-core cell portions and the input test vectors for the core cell partitions are combined into a single combined input test vector.
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申请公布号 |
US6751768(B2) |
申请公布日期 |
2004.06.15 |
申请号 |
US20010997658 |
申请日期 |
2001.11.29 |
申请人 |
AGILENT TECHNOLOGIES, INC. |
发明人 |
MURADALI FIDEL;JAARSMA NEAL C.;SUL CHINSONG;O'BRIEN GARRETT |
分类号 |
G06F11/00;(IPC1-7):G06F11/00 |
主分类号 |
G06F11/00 |
代理机构 |
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地址 |
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