| 发明名称 |
Method and apparatus for correcting a clock duty cycle in a clock distribution network |
| 摘要 |
A clock duty cycle correction circuit. The duty cycle correction circuit is located at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal.
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| 申请公布号 |
US6750689(B2) |
申请公布日期 |
2004.06.15 |
| 申请号 |
US20010823098 |
申请日期 |
2001.03.29 |
| 申请人 |
INTEL CORPORATION |
发明人 |
FLETCHER THOMAS D.;BARKATULLAH JAVED S. |
| 分类号 |
H03K5/15;H03K5/156;(IPC1-7):H03K3/017 |
主分类号 |
H03K5/15 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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