发明名称 |
Integrated circuit with vertical transistors |
摘要 |
A method of producing an integrated circuit having a vertical MOS transistor includes doping a substrate to form a layer adjacent to its surface and forming a lower doped layer serving as the transistor's first source/drain region. The transistor's channel region is formed by doping a central layer above the lower layer. A second source/drain region is formed by doping an upper layer above the central layer. The upper, central and lower layers form a layer sequence having opposed first and second faces. A connecting structure is formed on the first face to electrically connect the channel region and the substrate. The connecting structure laterally adjoins at least the central layer and the lower layer, and extends into the substrate. A gate dielectric and adjacent gate electrode are formed on the second face. |
申请公布号 |
US6750095(B1) |
申请公布日期 |
2004.06.15 |
申请号 |
US20010787966 |
申请日期 |
2001.05.29 |
申请人 |
INFINEON TECHNOLOGIES AG |
发明人 |
BERTAGNOLL EMMERICH;HOFMANN FRANZ;GOEBEL BERND;ROESNER WOLFGANG |
分类号 |
H01L21/8234;H01L21/336;H01L21/8239;H01L21/8242;H01L21/8246;H01L27/04;H01L27/088;H01L27/108;H01L27/112;H01L29/78;(IPC1-7):H01L21/824 |
主分类号 |
H01L21/8234 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|