| 摘要 |
Clocked full-rail differential logic circuits with sense amplifier and single-rail logic are activated by a delayed clock and include a sense amplifier circuit that is triggered by a second delayed clock. In Addition, according to the invention, the complementary logic function of the prior art is replaced by a single transistor appropriately sized to provide the complementary output. Consequently, the clocked full-rail differential logic circuits with sense amplifier and single-rail logic of the invention are smaller, less complex and are capable of operating efficiently under heavy load conditions without the increased size and the significant reduction in speed associated with prior art full-rail differential logic circuits.
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