METHOD AND PROCESSOR FOR MANAGING STATE INFORMATION IN PROCESSOR, AND DATA PROCESSING SYSTEM BY SAVING SOFT-STATE DATA WHEN PROCESS INTERRUPT IS RECEIVED

摘要

PURPOSE: A method and a processor for managing state information in the processor, and a data processing system are provided to minimize a processing delay caused by storing and recovering an architected state in response to an interrupt. CONSTITUTION: The processor includes at least one executing unit(204), an ISU(Instruction Sequencing Unit)(202) combined to at least one executing unit, a cache(212), and interface circuit(216). The cache stores volatile information forming a part of soft state of a process. The interface transfers the soft state to a system memory(118a) by responding to process interrupt reception of the processor.