发明名称 MULTIPLICATION REMAINDER OPERATION UNIT
摘要 PROBLEM TO BE SOLVED: To solve the problem wherein circuit scale is increased because a plurality of same circuits are necessary when using a parallel operation processing to carry out multiplication and remainder operation at high speed. SOLUTION: In a circuit for adding a partial product äΣ(Aj*B) *2^j (j=0,,,m-1)} to a temporary remainder u by using a value of a low ranking m bit (m is an integer 2 or more) of a multiplicand A and a multiplier B, a processing circuit for adding a modulo N and shifting by one bit is continuously connected at m stages to shift the low ranking m bit of the contemporary remainder u. This processing is repeated to operate a montgomery product of the multiplicand A and the multiplier B. This multiplication remainder operation unit can operate a multiple of the multiplier B by prohibiting one-bit shift of the processing circuit. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004164086(A) 申请公布日期 2004.06.10
申请号 JP20020326774 申请日期 2002.11.11
申请人 OKI ELECTRIC IND CO LTD;OKI TECHNOCOLLAGE INC 发明人 YAMADA KEI
分类号 G06F7/72;G09C1/00;(IPC1-7):G06F7/72 主分类号 G06F7/72
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