发明名称 Asynchronous multiple-order issue system architecture
摘要 An asynchronous circuit is described for processing units of data having a program order associated therewith. The circuit includes an N-way-issue resource comprising N parallel pipelines. Each pipeline is operable to transmit a subset of the units of data in a first-in-first-out manner. The asynchronous circuit is operable to sequentially control transmission of the units of data in the pipelines such that the program order is maintained.
申请公布号 US2004111589(A1) 申请公布日期 2004.06.10
申请号 US20030667152 申请日期 2003.09.16
申请人 发明人
分类号 G06F9/30;G06F9/38;(IPC1-7):G06F9/30 主分类号 G06F9/30
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