SEMICONDUCTOR MEMORY DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor memory device which realizes a high-speed sense operation and expansion of a sense margin by making the bit line amplitude of a sense amplifier section greater than the bit line amplitude of a memory cell array section and setting the precharge voltage of the bit lines of the sense amplifier section and the precharge voltage of the bit lines of the memory cell array section at different voltages. SOLUTION: P type transistors are employed for at least one or more of the first and second transistors constituting first and second precharge circuits installed between each of the complementary bit lines BL1 to BL2Bar (Bar signifies a bar of a reverse signal) and precharge potential supply lines and a third transistor constituting an equalizer circuit 5 installed between the complementary bit lines. COPYRIGHT: (C)2004,JPO