| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a multiprocessor system that can efficiently debug a plurality of processors while reducing the cost. <P>SOLUTION: A chip 1 comprises CPUs 7<SB>0</SB>and 7<SB>1</SB>, debug execution parts 8<SB>0</SB>and 8<SB>1</SB>, TAP controllers 9<SB>0</SB>and 9<SB>1</SB>, a selection circuit 10 and a terminal group including terminals 2 to 6. For a debug of only the CPU 7<SB>0</SB>, a TAP controller 100 sets a register 101 so that a signal S11 and a signal S12 become "H" and "L" respectively. For a debug of only the CPU 7<SB>1</SB>, the TAP controller 100 sets the register 101 so that the signal S11 and the signal S12 become "L" and "H" respectively. For a debug of both CPUs 7<SB>0</SB>and 7<SB>1</SB>, the TAP controller 100 sets the register 101 so that the signals S11 and S12 become "H" both. <P>COPYRIGHT: (C)2004,JPO |
