Method and apparatus for cache coherency between heterogeneous agents and limiting data transfers among symmetric processors

摘要

A system and method for improved cache performance is disclosed. In one embodiment, cache coherency schemes are categorized by whether or not they are capable of write-back caching. A signal may convey this information among the processors, allowing them to inhibit snooping in certain cases. In another embodiment, backoff signals may be exchanged among the processors, permitting them to inhibit certain unnecessary data transfers on a system bus.