发明名称 PLL CIRCUIT FOR PROVIDING STABLE SYNCHRONOUS SIGNAL AND METHOD FOR DETECTING PHASE THEREOF
摘要 PURPOSE: A PLL circuit for providing a stable synchronous signal and a method for detecting a phase thereof are provided to restrict the generation of unstable output synchronous signals by using a phase detection controller. CONSTITUTION: A PLL circuit for providing a stable synchronous signal includes a phase detector, a phase detection controller, a charge pump, a loop filter, a voltage controlled oscillator, and a frequency divider. The phase detector(110) is used for detecting a phase difference between the first input synchronous signal and an output synchronous signal according to a phase detection control signal and outputting a phase difference signal. The phase detection controller(120) is used for generating the phase detection control signal by using the first and the second input synchronous signals and the output synchronous signal. The charge pump(130) is used for supplying the current in response to the phase difference signal. The loop filter(140) is used for outputting a voltage in response to the supply amount of the current of the charge pump. The voltage controlled oscillator(150) is used for outputting an oscillation signal of a frequency in response to the output voltage of the loop filter. The frequency divider(160) is used for generating the output synchronous signal by dividing the frequency of the oscillation signal.
申请公布号 KR20040048740(A) 申请公布日期 2004.06.10
申请号 KR20020076699 申请日期 2002.12.04
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 MYUNG, JUN HYEONG
分类号 H03L7/089;(IPC1-7):H03L7/089 主分类号 H03L7/089
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