| 摘要 |
FIELD: automation and analog computer engineering. SUBSTANCE: proposed parity identifier that can be used for building functional assemblies of analog computers, automatic monitoring and control facilities, analog processors and provides for identifying equality of two time-varying analog signals x1, x2 both at x1 = x2 <> 0 and at x1 = x2 = 0 has adder, two relaters each incorporating comparator, closing and opening switches, and resistor. EFFECT: enlarged functional capabilities. 1 cl, 1 dwg
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