发明名称 |
Single poly EEPROM with reduced area |
摘要 |
An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.
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申请公布号 |
US6747308(B2) |
申请公布日期 |
2004.06.08 |
申请号 |
US20020334319 |
申请日期 |
2002.12.30 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
MITROS JOZEF C.;SPRINGER LILY;BUCKSCH ROLAND |
分类号 |
H01L27/115;H01L29/423;H01L29/788;(IPC1-7):H01L29/788 |
主分类号 |
H01L27/115 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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