| 摘要 |
The present invention provides a Delay Locked Loop circuit having: a delay device for generating at least one delayed clock signal from an input clock signal; a phase detector for comparing the delayed clock signal with the input clock signal; a first control device for generating a first control signal for influencing a delay time of the delay device; a device for generating a signal Q, whose frequency is proportional to the reciprocal of the delay time of the delay device; a device for evaluating the signal Q and generating an output signal; and a second control device for modifying the first control signal in accordance with the output signal. The present invention likewise provides a method for generating a control signal of a Delay Locked Loop circuit.
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