| 摘要 |
An improved memory device column decode apparatus and method is described that incorporates a reduced logic level column address decoder that fully decodes the column address and couples individual sense amplifiers to input or output busses with single pass transistors to provide for increased operation speed and lower sense amplifier resistance. The improved memory device column decode apparatus and method reduces column decode circuit and memory array size allowing for efficient memory array sizing and implementation. Additionally, the improved memory device column decode apparatus and method can incorporate fully decoded column select lines on a separate process layer of the memory array further reducing implementation size.
|
