发明名称 FLIP-FLOP CIRCUIT
摘要 PROBLEM TO BE SOLVED: To reduce the number of transistors, a circuit area and power consumption in a flip-flop circuit which includes an input part using a dynamic circuit and an output part using a static circuit and captures data during a term of pulse width shorter than a clock period. SOLUTION: An output of an inverter circuit INV1 comprising a latch circuit 2 connected to an output side of an input part 1 is used as an input of a control part 3. Thus, a control signal outputted from the control part 3 to the input part 1 is stabilized to suppress unwanted operations of circuit elements and to reduce useless power and further, a configuration of the control part 3 is also simplified at the same time, thereby reducing the number of constitutive transistors and the circuit area. COPYRIGHT: (C)2004,JPO
申请公布号 JP2004159315(A) 申请公布日期 2004.06.03
申请号 JP20030354177 申请日期 2003.10.14
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 HIRATA AKIO;GION MASAHIRO;NAKANISHI KAZUYUKI
分类号 H03K3/037;(IPC1-7):H03K3/037 主分类号 H03K3/037
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