| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device having an internal interconnection layout, capable of effectively utilizing an array area. <P>SOLUTION: A second metal interconnection (DMTS) is disposed in a dummy word line mapping region (DWLR), and a connection between a low-resistive metal interconnection (MTS), which constitutes a word line (WL) disposed in a normal word line mapping region (NWLRA) and a gate electrode interconnection (TG) of a lower layer is shifted. A memory cell gate electrode interconnection is disposed in a bit line intersection region (TWSA), and gates for an access transistor of a memory cell are interconnected to each other, to form an intersection structure of a bit line, by using metal interconnections (MTFB, MTSB) of the upper layer. <P>COPYRIGHT: (C)2004,JPO |
