| 摘要 |
A low voltage detection (LVD) system for a logic device includes a first LVD circuit ( 110 ) to provide an indicator when a supply pin voltage ( 109 ) falls below a first voltage level, and a second LVD circuit ( 116 ) to provide an interrupt ( 118 ) when the supply pin voltage falls below a second voltage level. In one embodiment, the second LVD circuit consumes more power than the first LVD circuit, and is therefore selectively enabled. In one embodiment, when the supply pin voltage is between the first and second voltage levels and the logic device is in a stop or low power mode, the second LVD circuit is periodically enabled to monitor the supply pin voltage. After the supply pin voltage falls below the second voltage level, the logic device is placed in a safe state where the logic device is inhibited from acknowledging interrupts until the supply pin voltage rises above the first voltage level. |
